1. Field of the Invention
The present invention relates to a memory apparatus and a related testing method, and more particularly, to an error correction code (ECC) memory and a related testing method.
2. Description of the Prior Art
The memory is an essential electronic component in electronic products. However, the data accuracy of the memory may decrease if the manufacturing process of the memory has defects or as its access times increase. In order to solve this problem of causing errors in data, an error correction codes (ECC) logic circuit is usually adopted to repair the erroneous data.
In general, when a test is performed on an ECC memory, the ECC logic circuit is enabled, which is also called as the ECC-on test. When a storage block with an identical address in the memory has multi-bit error, such error cannot be detected if a common testing algorithm is adopted. In addition, current testing methods for the ECC memory are unable to know the error number and the error status of the memory, and therefore an error tolerance is unable to be controlled.